Monolithic transformers are used in on-chip radio frequency (RF) integrated circuits (ICs) to perform a range of functions including impedance matching, signal coupling and phase splitting. Monolithic transformers provide a number of advantages for the circuit designer over conventional transformers including lower power consumption and higher packaging density. Monolithic transformers enable power amplifiers to be fabricated by standard CMOS processes. However, power levels obtainable based on existing fully integrated amplifiers using silicon as the substrate are too low to be considered for wireless applications. This is due to power losses caused by eddy currents induced in the silicon substrate by electromagnetic fields associated with coils of the transformer.
In order to reduce power losses, a variety of fabrication methods have been proposed including special wafer-processing techniques including thinning of the silicon substrate. This technique is costly, however, and not readily compatible with foundry processing technologies. Furthermore, additional costs are associated with this technique.
Current fabrication techniques for monolithic transformer structures result in the primary and secondary coils being formed to have unequal physical lengths, resulting in a difference between the values of inductance of the coils. Furthermore, in the case of stacked transformer structures, differences in metallization thicknesses and distances between respective coils and the silicon substrate also cause discrepancies in transformer performance.
Examples of known integrated transformer structures include planar transformer structures that rely on coupling between coils located primarily in the same plane, ie lateral (or ‘side’) coupling between coils. US2003/0071706 discloses such a structure.
FIGS. 1(a) and (b) show prior art transformer structures of the planar and stacked type, respectively. The structures show transformers having, respectively, two and four turns per primary and secondary coil. FIGS. 2(a) and (b) are exploded views of the structures of FIGS. 1(a) and (b) respectively.
Planar transformers rely on coupling between coils in a lateral (or ‘horizontal’) direction. Structures of the stacked type rely on coupling between coils located in parallel spaced apart planes, i.e. transverse (or ‘vertical’) coupling. US2004/0056749 discloses structures of the stacked type.
Lee (S.-G. Lee, “Area efficient and symmetric design of monolithic transformers for silicon RF ICs,” Proceedings of the IEEE Region 10 Conference, 1999, pages 880-882) proposed an integrated transformer structure having the feature of mixed coupling between primary and secondary coils. The structure proposed by Lee exhibits side-coupling (hereinafter referred to as ‘lateral coupling’) and vertical-coupling (hereinafter referred to as ‘transverse coupling’). Mixed coupling was suggested to provide the best performance in terms of symmetry, area efficiency and insertion loss.
The performance of mixed coupling devices is generally better than that of devices relying on only lateral or transverse coupling between coils. However, further improvements in transformer performance are highly desirable.